Traditional CMOS (complementary metal oxide semiconductor) techniques include process flows for constructing planar FET devices. With planar FETs, increased transistor density can be achieved by decreasing the pitch between transistor gate elements. However, with planar FET devices, the ability to decrease gate pitch is limited by the required gate length, spacer thickness, and source/drain size. In recent years, there has been significant research and development with regard to vertical FET devices, which decouple the gate length from the gate pitch requirement and enable scaling of transistor density. In general, vertical FET devices are designed to have gate structures that are formed on multiple sides of a vertical channel structure (e.g., a vertical semiconductor fin or vertical nanowire). With vertical FET devices, scaling is determined by how closely conductive contacts to source and drain regions can be placed.
In general, vertical FET devices employ doped source and drain regions, wherein a doped source region for a vertical FET can be formed on top of a vertical semiconductor fin, and wherein a doped drain region can be formed underneath the vertical semiconductor fin. In addition, a vertical drain contact of the vertical FET device is disposed adjacent to the vertical semiconductor fin as an elongated bar contact. The vertical drain contact is formed to make contact to an upper surface of the underlying drain region, and is disposed at a sufficient distance from the vertical semiconductor fin so that the vertical drain contact does not electrically short to the vertical metal gate structure formed on the vertical semiconductor fin. What this effectively means is that the current path through the doped drain region between the vertical drain contact/drain region interface and the drain region/channel junction interface, is comprised entirely of doped semiconductor material. This current path through the doped drain region, if relatively long, can result in increased series resistance of the drain, which in turn reduces a total drive current of the vertical FET device. Furthermore, if the vertical FET channel width is large (which, for a vertical FET, means patterning a long semiconductor fin), then the total drain resistance is high toward an opposite end of the semiconductor fin which is not adjacent to the vertical drain contact. This results in a voltage drop across the device width and, therefore, a Vds non-uniformity across the device width, with Vds being smaller at the opposite end of the semiconductor fin as compared to the Vds at the end of the semiconductor fin adjacent to the drain contact, which also reduces a total drive current of the vertical FET device.